As described in JP 2001-7155 A, a flip-chip bonding is conventionally known as a mounting method for mounting a semiconductor element such as a semiconductor integrated circuit element on a wiring board.
As the wiring board used in the flip-chip bonding, a wiring board formed by a buildup method is known. FIG. 4 is a schematic cross-sectional view showing a conventional wiring board 20 formed by the buildup method. FIG. 5 is a horizontal cross-sectional view of the wiring board 20 taken along line I-I in FIG. 4.
As shown in FIG. 4, the conventional wiring board 20 includes buildup insulating layers 12 and buildup wiring layers 13 alternately laminated on upper and lower surfaces of a core substrate 11.
A core conductor layer 14 made of copper foil or a copper plating layer is adhered to the upper and lower surfaces of the core substrate 11. In addition, a number of through-holes 15 are formed so as to extend from the upper surface to the lower surface of the core substrate 11, and the copper plating layer serving as a part of the core conductor layer 14 is adhered to an inside of the through-hole 15. The through-hole 15 is filled with a resin.
A plurality of via-holes 16 are formed in each buildup insulating layer 12. The buildup wiring layer 13 made of a copper plating layer is formed on and adhered to a surface of the buildup insulating layer 12 including the via-holes 16.
The vertically adjacent buildup wiring layers 13, 13 are electrically connected to each other through the via-holes 16. The buildup wiring layer 13 is electrically connected to the through-holes 15. A part of the outermost buildup wiring layer 13 located on a side of an upper surface of the wiring board 20 is formed as circular semiconductor element connection pads 17 which are electrically connected to electrodes T of a semiconductor element S. These semiconductor element connection pads 17 are arranged in a lattice-like form so as to correspond to the electrodes T of the semiconductor element S, in a semiconductor element connection pad formation region A which is a square region corresponding to the semiconductor element S. A part of the outermost buildup wiring layer 13 located on a side of a lower surface of the wiring board 20 is formed as circular external connection pads 18 which are each electrically connected to a wiring conductor of an external electric circuit board (not shown). These external connection pads 18 are arranged in a lattice-like form.
Solder resist layers 19 are adhered to the outermost buildup insulating layer 12 and the buildup wiring layer 13 formed thereon except for the exposed semiconductor element connection pad 17 and external connection pad 18. A soldering bump B is welded to the semiconductor element connection pad 17 which is not covered with the solder resist layer 19. The electrode T of the semiconductor element S is electrically connected to the exposed semiconductor element connection pad 17 through the soldering bump B. The exposed external connection pad 18 which is not covered with the solder resist layer 19 is connected to the wiring conductor of the external electric circuit board (not shown) through a soldering ball.
In the meantime, in order to ensure sufficient power supply from the wiring board 20, many semiconductor elements S have a terminal arrangement in which a number of grounding and power supply electrodes T are provided in a center of its lower surface, and a number of signal electrodes T are provided in an outer peripheral portion of its lower surface.
When such a semiconductor element S is mounted on the wiring board, as shown in FIG. 5, grounding through-holes 15G and power supply through-holes 15P are provided in a region X opposed to the semiconductor element connection pad formation region A, at a high arrangement density. Meanwhile, signal through-holes 15S are provided in an outer peripheral portion of the core substrate 11 outside the region X, at a low arrangement density. Since the grounding through-holes 15G and the power supply through-holes 15P are provided in the region X opposed to the semiconductor element connection pad formation region A, at the high arrangement density, it is possible to connect the grounding semiconductor element connection pad 17 to the grounding through-hole 15G, and the power supply semiconductor element connection pad 17 to the power supply through-hole 15P within a short distance.
Furthermore, the grounding external connection pads 18 and the power supply external connection pads 18 are arranged in a center of the lower surface of the wiring board 20. Thus, it is possible to connect the grounding through-hole 15G to the grounding external connection pad 18, and the power supply through-hole 15P to the power supply external connection pad 18 within a short distance. As a result, an inductance is low in each of current paths for connecting the grounding semiconductor element connection pad 17 to the grounding external connection pad 18, and the power supply semiconductor element connection pad 17 to the power supply external connection pad 18, so that the power can be sufficiently supplied to the semiconductor element S.
As shown in JP 2011-159734 A, according to the conventional wiring board, the arrangement density of the through-holes 15 is higher in the region X of the core substrate which is opposed to the semiconductor element connection pad formation region A, and is lower in the region outside the region X. However, behaviors of thermal expansion and thermal shrinkage, and stiffness differ between the region having the high arrangement density of the through-holes 15 and the region having the low arrangement density thereof. The difference in behaviors of the thermal expansion and thermal shrinkage, and the difference in stiffness become a factor that causes warpage in the wiring board 20 when the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 17 through the soldering bump B.
Therefore, when the semiconductor element S is mounted on the conventional wiring board 20, the upper surface of the wiring board 20 is warped and recessed warpage is generated as shown in FIG. 6. When such recessed warpage is generated, a distance is reduced between the electrode T of the semiconductor element S and the semiconductor element connection pad 17 formed in an outer peripheral portion in the semiconductor element connection pad formation region A, so that the soldering bump B is severely crushed. When the soldering bumps B adjacent to each other are severely crushed, these soldering bumps B come in contact with each other to cause an electrical short circuit. As a result, the semiconductor element S cannot be normally operated.